Lead-containing solders have been used extensively in microelectronic interconnect structures between various packaging levels. Since the RoHS enforcement date of July 1, 2006 by the EU is rapidly approaching, the transition to Pb-free solders is accelerating in the electronics industry.1
At IBM, considerable R&D efforts on Pb-free solders technology were conducted well before the RoHS and WEEE Directives were enacted by the EU, as noticed in the early publication and patent literature.2-5 An example of the application of Pb-free technology within IBM is the usage of Bi-Sn eutectic solder for low-temperature wave soldering of plated through holes (PTH) in advanced multilayer PCBs since the early 1970s.6-7 IBM’s early work led to the National Center for Manufacturing Sciences (NCMS) Pb-free solder project, the first industry-wide joint effort to search for Pb-free solders. When the final report of the NCMS Pb-free project was published in 1997, it was dedicated to the memory of Roger Wild (former IBMer) for his pioneering work on Pb-free soldering technology at IBM.8
Fundamentals
Recently, worldwide R&D efforts on Pb-free solder alloys have identified several promising candidates for different soldering applications, as listed in Table 1. Two major Pb-containing solders, eutectic 63Sn-37Pb and Pb-rich solders used for SMT and flip chip or C4 (controlled collapse chip connection) solder bumps are also included in Table 1. It should be noted that the compositions of most Pb-free solder candidates are Sn-rich solders that contain more than 90% Sn. This suggests that the physical, chemical, and mechanical properties of the proposed Pb-free solders are heavily influenced by the properties of pure Sn, as opposed to eutectic Sn-Pb, which microstructure consists of a mixture of Sn-rich and Pb-rich lamellar phases. Pure Sn is polymorphic, capable of existing as three different crystal structures (∝, β, γ) depending on temperature and pressure.9 Since the white tin phase (β-Sn) has a body-centered tetragonal (BCT) crystal structure in contrast to the face-centered cubic (FCC) structure of Pb, the physical and mechanical properties of white tin are less isotropic and more difficult to mechanically deform in comparison to Pb. Since the white Sn crystal is optically birefringent, polarized light microscopy can be used to distinguish the orientation of β-Sn dendrite structures in Pb-free solders.10
The melting point of most Pb-free commercial solders is within the range of 208º to 227ºC, which is about 30ºC higher than the melting point of eutectic Sn-Pb at 183ºC. The higher melting point has serious implications on the performance of packaging materials and assembly processes, and can affect the integrity and/or reliability of Pb-free microelectronic packages. Another important issue associated with the proposed Pb-free solders is the difficulty of maintaining solder melting-point hierarchy, which has been well established with Pb-containing solders. With the proposed Pb-free solders, the maximum differentiation in solder melting temperatures between any two package levels is less than 30ºC. The process control, during successive multiple soldering processes with Pb-free solders, becomes more challenging and its impact on solder joint and package reliability is not yet well understood.
Among the several Pb-free solder candidates, the near-ternary eutectic Sn-Ag-Cu (SAC) alloy compositions with melting temperatures around 217ºC is the consensus solder alloy for SMT card assembly, including BGA solder joints, while the eutectic Sn-Cu or Sn-Ag-Cu alloy is a promising choice for Pb-free flip chip applications.11-14
Pb-free Ceramic Ball Grid Arrays
IBM’s development team conducted evaluations, using a number of criteria, in the early phase. Sn-3.8Ag-0.7Cu (SAC in wt. %) was selected based on its excellent wettability to I/O pads, stable microstructure of solder joints, superior ball shear strength, and the excellent thermal-mechanical fatigue (TMF) behavior of assembled modules subjected to accelerated thermal cycling.15 Further work with SAC confirmed that it was an optimal replacement alloy for Sn-Pb CBGAs for both 1.27- and 1.00-mm pitch.16
Reliability evaluation was performed with co-fired multilayer 9211 (alumina-based) ceramic test vehicles (32.5-mm square to 42.5-mm square, with thickness ranging from 1.50 to 3.70 mm). Five ceramic modules were attached by using SAC solder balls to a FR4 test card (6S4P, 229 × 279 mm). A typical cross section of a CBGA solder joint connecting a ceramic module to a Cu pad on a PCB (as-joined) is shown in Figure 1. Standard accelerated thermal cycle (ATC) testing (from 0° to 100°C, with 2 cycles/hr.) was used on the assemblies with a periodic, 4-point resistance measurement. An increase in resistance of 10 Ω or greater was used to define a failure. Table 2 summarizes the MTF data of Pb-free CBGA modules in comparison with the Sn-Pb, IBM dual-melt structure as a benchmark. The N50s were calculated by fitting a lognormal distribution to the fatigue data. All of the SAC alloy test vehicles produced well-controlled fatigue life as indicated by the small sigma. The SAC alloy has almost twice the fatigue life of the dual alloy Sn/Pb structure, for the same form factor. The full melting of SAC balls during assembly causes a smaller joint height with the SAC structure than the Sn-Pb structure. In spite of the unfavorable ratio of joint heights (1:2), the SAC alloy demonstrates the superior fatigue properties over the Sn-Pb for the same form factor. The TMF performance of SAC, combined with the relative lack of complexity in manufacturing these assemblies, makes the Pb-free CBGA technology a winner on all fronts.
Pb-free PBGA
The transition to Pb-free soldering technology has been juxtaposed on other market forces driving PBGA packaging toward high-performance, higher I/O, and high-reliability applications. The confluence of all these factors in time has made the development of Pb-free organic packaging technology a challenging watershed to cross. The higher reflow temperatures associated with Pb-free packaging technology have mandated the use of new organic packaging materials with improved water absorption characteristics, reduced CTE’s, and improved thermal stability. Higher reflow temperatures and the accompanying evolution toward higher I/O and larger chip sizes result in higher package stresses and place more stringent requirements on interfacial adhesion within electronic package structures. The stresses fostering package delamination derive from CTE mismatch, from increased steam pressurization within the packages, due to the presence of absorbed moisture, and in the case of flip chip packaging from the full melting of the C4 bumps within the underfill encapsulation. The choice of solderable surface finish and its bearing on solder joint fragility is a significant concern across the industry at this time. In this regard, IBM has chosen Cu pad structures as the surface finish for most of its packaging requirements. Successful Pb-free packaging, capable of passing stringent reliability testing, has mandated improved materials and significant interfacial adhesion augmentation.
Wire-Bond, PBGA Packaging. IBM has produced Pb-free wire-bond PBGA packages since early 2002 in both glob-top and overmolded configurations, and expects to be qualified to produce Pb-free and halogen-free products by the end of 2005. Package sizes range from 15 to 45 mm, with 1.27- and 1.0-mm BGA pitch. To achieve these results, new glob-top and overmold materials were developed in close working relationships with materials suppliers. The new materials have improved adhesion and moisture absorption characteristics, together with improved wire sweep processing characteristics capable of accommodating complex wire-bond trajectories.
Flip Chip, PBGA Packaging. Flip chip packaging is associated with a broader range of packaging challenges in achieving a successful transition to Pb-free soldering technology. New BLM (Ball Limiting Metallurgy or UBM) structures are required to accommodate the use of high Sn, Pb-free, solders. The full melting, Pb-free, C4 structures provide for higher internal package stresses during reflow because the bump volume increase associated with the melting process is constrained by the underfill encapsulant. The use of new underfill materials was required to meet the Pb-free reflow requirements. In addition, new thermal solutions and lower CTE laminate materials were incorporated to improve package reliability as the simultaneous evolutionary transition was made toward higher-performance modules. Package qualifications have been successful with the new organic material set and solder alloys. Flip chip PBGA products are now qualified from 15 to 42.5 mm for both 225- and 200-µm C4 pitch with 1.27- and 1.0-mm BGA pitch. Future extension to 55-mm package size is anticipated in the near future.
Pb-free Flip Chip Solder Plating
IBM is developing a Pb-free C4 solder bumping process for flip chip applications in response to customer requirements and environmental regulations. IBM has been plating C4 solder (97Pb-3Sn) for more than 9 years using a TiW/CrCu/Cu BLM structure.
The development approach for Pb-free C4 plating incorporated several key ground rules. A multifunctional team including development, process, equipment, quality, reliability and product engineering, analysis, research, and manufacturing was formed. Minimal changes to the existing successful BLM structure were desired. The new Pb-free process is designed to maximize use of the existing production line capital infrastructure and process for ease of manufacturing.
Two key components of the Pb-free C4 structure are the BLM and the C4 metallurgy. It is well known that the Pb-free, Sn-rich solders are highly reactive and, therefore, require a robust barrier metallurgy in the BLM to withstand aggressive high-temperature-storage (HTS) and electromigration requirements. IBM has been using a Ni barrier for other products, and chose to incorporate Ni as the barrier for Pb-free C4. For the solder metallurgy, we evaluated Sn-Cu as well as Sn-Ag-Cu (SAC) constructions. The evaluation criteria included ease of manufacturing, quality and reliability. From a reliability standpoint, the SAC and Sn-Cu solders performed equivalently. With our current tool set, the greater ease of manufacturing and better bump quality of Sn-Cu resulted in our choice of Sn-Cu over SAC. The construction IBM subsequently qualified for production is a TiW/CrCu/Cu/Ni BLM with Sn-Cu solder metallurgy, as shown in Figure 2. The first Pb-free C4 application that IBM qualified and put into production is a chip-on-flex one. We completed a production line qualification as well as a reliability assessment. There were no C4 fails in deep-thermal-cycling (DTC), HTS, low-temperature-storage (LTS), temperature/humidity and bias (THB), high-temperature-operating-life (HTOL) or ATC stresses. Electromigration performance of this Pb-free C4 was better than expected, between eutectic Sn-Pb solder and 97Pb-3Sn solder in performance. This application is now in production at IBM.
The key challenge for the future will be to provide Pb-free C4 bumps at 150-µm pitch and below. IBM is currently developing solutions for that application space. IBM has developed, qualified, and is in production for Pb-free C4 bumps. Qualification for additional applications is in progress, with a good prognosis for continued success.
Pb-free Wafer Bumping
Multiple transitions are presently occurring in the wafer bumping industry. Among these are increased wafer size from 200 to 300 mm, decreased bump size and pitch, alloy change from eutectic Pb-Sn to Pb-free, and the continued growth of flip chip vs. wire bond. At the same time, the demand for lower costs, finer pitch, and higher quality is unrelenting. In September 2004, IBM and SUSS MicroTech announced a new wafer bumping technology called “C4NP,” short for Controlled Collapse Chip Connect New Process, to address these challenges.
C4NP grew out of earlier work at IBM Research in which a new injection-molded solder (IMS) process produced advanced thermal interfaces. It was quickly realized that IMS could readily be applied for making solder interconnect structures. A parallel process, C4NP fills molten solder into small cavities in a bump template that matches the I/O footprint of a silicon wafer. After the solder is solidified, an inspection step ensures that all the cavities are properly filled. Separately, wafers are prepared with the appropriate BLM compatible with the desired solder alloy. The last step actually bumps the wafer, namely aligning the filled bump template and joining it in mirror-image fashion to the silicon wafer above the solder reflow temperature. This transfers the solder volumes from the cavities to the wafer. The bump templates are reusable, keeping costs low. Several advantages can be listed for C4NP:
* Alloy flexibility including multicomponent Pb-free alloys;
* No volume change from deposition to final bump; extendible to fine bump size and pitch;
* Same tool set for both 200-mm and 300-mm wafers;
* Low material costs in comparison to paste, preform, or chemical solution;
* Optimal yields by bump template inspection before transfer to wafer;
* Rapid turn-around time by prefilling bump templates ahead of wafer completion;
* Efficient solder usage for environmental and economic benefits;
* Extendability to finer pitch;
* Process simplicity similar to stencil printing.
As seen in Table 3, a comparison of other established bumping processes explains why C4NP is creating excitement in the industry. Considering the challenges ahead, the timing of a new bumping technology that combines high-end capabilities with low-end costs may be considered auspicious. More than 40 years ago, IBM first introduced C4 technology. C4NP, as the latest version, should provide a cost-effective solution to meet present and future Pb-free wafer bumping needs.
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